1. Field of the Invention
The present invention relates to design of closely spaced semiconductor devices. In particular, the present invention relates to design of closely spaced dual-gate semiconductor devices useful, for example, in non-volatile memory applications.
2. Discussion of the Related Art
As the dimensions of semiconductor devices continue to diminish, dopant diffusion has become a serious hurdle to proportionally scale existing devices to take advantage of the smaller dimensions. One example of the dopant diffusion problem is illustrated, for example, by conventional NMOS field effect transistor (FET) 100 of FIG. 1. In FIG. 1, NMOS FET 100 is formed on a monocrystalline semiconductor substrate 101. Typically, after dielectric layer (“gate dielectric layer”) 102 and gate electrode 103 are formed, using conventional deposition, photolithographical and etching techniques, N-type dopants (e.g., phosphorus or arsenic) are introduced (e.g., by ion implantation) into exposed areas 104a and 104b of substrate 101, self-aligned to gate electrode structure 103 to form a source region and a drain region. The region at the surface of semiconductor substrate 101 protected by gate electrode 103 forms a channel region which, during operation, selectably provides a conductive path between source and drain regions 104a and 104b when a suitable voltage relative to source region 104a is imposed on gate electrode structure 103. Thermal steps in the manufacturing process subsequent to the step introducing dopants into source and drain regions 104a and 104b cause the dopants to diffuse laterally under gate electrode 103, as indicated in FIG. 1. The dopant diffusion has the effect of shortening the length of the channel region (“channel length”). However, so long as source and drain regions 104a and 104b remain separated by a minimum distance, the resulting structure is able to operate as an NMOS FET.
As the dimensions of semiconductor devices continue to diminish, the length of the channel region before dopant diffusion diminishes proportionally, bringing the implanted source and drain regions 104a and 104b closer together. However, without a change in the subsequent thermal steps, the shortening resulting from dopant diffusion is not changed, so that the channel length of the transistor may become unacceptably short for proper device operation.
FIG. 2 shows another example in which dopant diffusion affects device scaling. FIG. 2 shows memory transistors 200a-200d in a NAND “flash” string structure. As shown in FIG. 2, memory transistors 200a-200d include control and floating gate electrodes 201a-201d and source and drain regions 202a-202e, which may be created by implanting dopant ions into in monocrystalline semiconductor substrate 204. Control and floating gate electrodes 201a-201d are formed over a thin tunnel oxide layer 203 (represented by tunnel oxide structures 203a-203d), each including a floating gate electrode and a control gate electrode separated by an dielectric layer between the polysilicon layers forming the floating and control electrodes. The charge stored in the floating gate electrode controls the conductivity type in the channel region formed on the surface of semiconductor substrate 201 under the floating gate electrode. The control gate electrode controls storing or removing the charge stored in its associated floating gate electrode. Memory transistors 200a-200d of FIG. 2 are difficult to scale because of dopant diffusion into the channel regions, in a manner substantially similar to the dopant diffusion problem discussed above with respect to NMOS FET 100 of FIG. 1.
The dopant diffusion problem is even more acute in thin film transistors (TFTs) where the channel, source and drain regions are formed in a polycrystalline material (e.g., polysilicon or amorphous material, such as amorphous silicon) in which dopant diffusion is many times enhanced compared to material such as the monocrystalline silicon substrates of FIGS. 1 and 2.
Accordingly, there is a need for overcoming scaling limitations caused by dopant diffusion in devices having the smaller device dimensions achieved today.